Cogenda provides standard cell library development services at 130nm - 65nm technology nodes at the wafer fab of the customers' choice. A basic library includes
Additional cells can be added upon request.
Radiation tolerance designs are verified with Cogenda's fully-physical SEE simulation framework.
Fig. 1 TCAD model of a DICE flipflop used for validating the SEU-hardness of the design.
Fig. 2 TCAD simulated voltage waveform of the storage nodes in a DICE flipflop, showing prompt recovery after hit by a heavy ion.
Extensive simulations have been performed at the computing cluster at Cogenda to optimize the layout of circuit cells for SEL immunity and cross-section minimization. Through many design-simulate iterations, hardness is achieved without incurring excessive over-design.
Cogenda uses an in-house automation flow for cell library creation, and provides a set of vendor-neutal EDA views that can be used in the standard ASIC flow of all major EDA vendors.
|Netlist for LVS||CDL|
|Abstract physical library||LEF|
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Cogenda can provide test chip and test keys for radiation hardness tests. A typical design cycle targets a first tape-out in six months.